1. Field of the Invention
The present invention relates to a memory device.
2. Description of the Related Art
As memory devices, volatile memory devices (e.g., a SRAM, a DRAM, etc.) and non-volatile memory devices (e.g., an EEPROM, a FRAM, a PRAM, a ReRAM, a MRAM, etc.) are known. Among these memory devices, the DRAM and the FRAM include as a minimum configuration unit (memory cell) a transistor and a capacitor having a general structure, and the PRAM, the ReRAM, and the MRAM generally include as a minimum configuration unit a transistor and an element whose electric resistance is changed with the application of voltage. Therefore, these memory devices can be manufactured with a simple circuit configuration.
FIG. 1 shows a configuration of the memory cell of the DRAM. In the following, writing of data, refresh, and reading of data in a memory cell 11 are described.
(1) Writing of Data
When voltage is applied to a word line 11a and a select transistor 11b is turned on, charges are accumulated in a paraelectric capacitor 11c and data element “1” is written in the memory cell 11. On the other hand, when voltage is not applied to the word line 11a and the select transistor 11b is turned off, charges are not accumulated in the paraelectric capacitor 11c and data “0” element is written in the memory cell 11. At this time, because the charges accumulated in the paraelectric capacitor 11c decrease with time and become zero, it is necessary to refresh the memory cell 11.
(2) Refresh
The refresh refers to writing at a predetermined time interval with respect to the memory cell 11 in which the data element “1” has been written. Note that a dummy cell 12 is connected to a dummy capacitor 12c whose capacity is half the size of the paraelectric capacitor 11c, and it generally has no charges accumulated therein.
(3) Reading of Data
In a case where the data element “1” is written in the memory cell 11, more than half charges are held even if a small amount of time passes. Accordingly, when voltage is applied to the word lines 11a and 12a and the select transistor 11b and a dummy transistor 12b are turned on, charges are accumulated in the paraelectric capacitor 11c and the dummy capacitor 12c. However, many charges are moved by the dummy capacitor 12c. A sense amplifier 13, which is connected to the memory cell 11 and the dummy cell 12 via bit lines 11d and 12d, detects the movement of the charges and determines that the data element “1” has been written in the memory cell 11. As a result, the data element “1” is read. At this time, the charges accumulated in the dummy capacitor 12c are promptly reduced to zero.
Furthermore, in a case where the data element “0” is written in the memory cell 11, when the select transistor 11b and the dummy transistor 12b are turned on, many charges are moved by the paraelectric capacitor 11c. The sense amplifier 13 detects the movement of the charges and determines that the data element “0” has been written in the memory cell 11. As a result, the data element “0” is read. At this time, the charges accumulated in the paraelectric capacitor 11c and the dummy capacitor 12c are promptly reduced to zero.
As described above, the DRAM is a memory that holds data only when voltage is being applied, and it is called a volatile memory.
FIG. 2 shows a configuration of the cell of the FRAM. Next, the writing and the reading of data in the cell are described.
(1) Writing of Data
When voltage is applied to a bit line 21a, a word line 21b, and a plate line 21c in the order (t1<t2<t3) shown in table 1, the data element “0” is written in a cell 21. In other words, in t2, the data element “0” refers to where the voltage of a ferroelectric capacitor 21d on the side of a transistor 21e is lower than that on the side of the plate line 21c. Then, even if the power is turned off (t3), charges are accumulated in the ferroelectric capacitor 21d to hold data therein. Therefore, a non-volatile memory is provided.
TABLE 1t1t2t3VOLTAGE APPLIED TO BIT LINE[V]000VOLTAGE APPLIED TO WORD LINEONONOFFVOLTAGE APPLIED TO PLATE LINE[V]0VCC0
Furthermore, when voltage is applied to the bit line 21a, the word line 21b, and the plate line 21c in the order shown in table 2, the data element “1” is written in the cell 21. In other words, in t2, the data element “1” refers to where the voltage of the ferroelectric capacitor 21d on the side of the transistor 21e is higher than that on the side of the plate line 21c.
TABLE 2t1t2t3VOLTAGE APPLIED TO BIT LINE[V]0VCC0VOLTAGE APPLIED TO WORD LINEONONOFFVOLTAGE APPLIED TO PLATE LINE[V]000
(2) Reading of Data
First, after the voltage 0 V is applied to the bit line 21a and the word line 21b is turned on, Vcc is applied to the plate line 21c. In a case where the data element “0” has been written in the cell 21, the movement I0 of charges shown in FIG. 3A causes the bit line 21a to be charged up to V0. Furthermore, in a case where the data element “1” has been written in the cell 21, the movement I1 of charges greater than I0 as shown in FIG. 3B causes the bit line 21a to be charged up to V1. Here, a sense amplifier 22 having an intermediate potential Vref between V1 and V0 is connected to the bit line 21a. When a potential is greater than Vref, the sense amplifier amplifies it up to Vcc and reads the same as the data element “1.” Also, when the potential is smaller than Vref, the amplifier recognizes it as 0 V and reads the same as the data element “0.”
Furthermore, even if the capacitor connected to the memory cell in the DRAM is replaced by an element whose electric resistance is changed with the application of voltage, the DRAM serves as a memory device. If the element is capable of holding the electric resistance, the DRAM serves as a non-volatile memory similar to the FRAM.
As a non-volatile memory of this type, a phase-change memory (PRAM) is provided (see Patent Document 1).
FIG. 4 shows the memory cell of the PRAM. A phase-change material 41a can change its phase into either a polycrystalline state or an amorphous state. In the case of the amorphous state, current passing through the phase-change material 41a becomes small, which is set as “0.” Furthermore, the phase-change material 41a turns to the polycrystalline state when it is supplied with a relatively small current and held at a crystallization temperature below its melting point in the amorphous state. At this time, the current passing through the phase-change material 41a becomes large, which is set as “1.” On the other hand, the phase-change material 41a turns to the amorphous state when it is rapidly cooled after being supplied with a relatively large current and melted. Generally, the phase change from the amorphous state to the polycrystalline state takes more time than that from the polycrystalline state to the amorphous state, but it is controlled by the length of pulse voltage to be applied. The principle of operation using such a function of changing and holding an electric resistance is also applicable to the ReRAM and the MRAM as other non-volatile memory devices. Here, instead of using the phase-change material of the PRAM, the ReRAM is generally made of a transistor and an element holding either the insulation body or the semiconductor of a transition metal oxide between electrodes, and the MRAM is made of a magnetic tunnel junction element and a transistor. Among these non-volatile memories, the PRAM is expected to become a non-volatile memory device for facilitating high integration.
FIG. 5 shows a general structure of a (planar-type) transistor. The transistor 50 has a gate electrode 52, a gate insulation film 53, a source electrode 54a, a drain electrode 54b, and a semiconductor layer 55 laminated on a substrate 51 one upon another.
Recently and continuing, attention is given to organic TFTs from the viewpoint of cost reduction in various electronic devices such as displays and IC tags. In order to put such electronic devices to practical use, it is necessary to ensure an operating speed satisfying the practical use. However, because the carrier mobility μ of organic semiconductors is generally much smaller than that of silicon semiconductors, it is difficult for the organic semiconductors to respond at high speed. The relationship between a cutoff frequency fc as an index of a TFT operating speed, a mutual conductance gm, and a gate capacity Cg is expressed by a formula fc∝gm/Cg, wherein Cg is proportional to the gate electrode 52, the gate overlap D formed between the source electrode 54a and the drain electrode 54b, and the channel length L. In addition, because gm is generally proportional to μ/L, it is necessary to reduce L and D as a device structure so as to improve fc. However, in order to make L several μm or smaller and perform patterning on the source electrode 54a and the drain electrode 54b, it is generally necessary to undergo complicated processes and install expensive manufacturing apparatuses, resulting in an increase in manufacturing costs. Furthermore, where the substrate 51 is likely to contract like a resin film in particular, the larger the areas of the gate electrode 52, the source electrode 54a, and the drain electrode 54b are, the more difficult it is for the gate electrode 52, the source electrode 54a, and the drain electrode 54b to be aligned so as to be almost not overlapped with each other. In the case of a silicon TFT, the gate electrode 52 on which minute patterning is performed using photolithography is generally used as a mask and an ion injection process is used to perform self-alignment to make the gate overlap D as small as possible. However, this results in an increase in manufacturing costs. Accordingly, it is difficult to manufacture a high-speed TFT at low cost. That is, it is difficult to manufacture a memory device capable of operating at high speed.
Moreover, when the DRAM is refreshed and the data of the FRAM are read in a case where a transistor is applied to a memory device, the data element “1” or the data element “0” is determined according to the amount of charges accumulated in a capacitor connected to the transistor relative to a predetermined reference value. As shown in FIG. 6, on the other hand, a transistor 60 having the gate overlap D includes parasitic capacities 63a between a gate electrode 61 and source and drain electrodes 62a and 62b. When the transistor 60 is applied to a memory device, the parasitic capacity 63 is charged as soon as a word line is turned on at the time of the refresh and the reading of data. Accordingly, in the case of the DRAM shown in FIG. 1, the balance between the capacity of the paraelectric capacitor 11c and that of the dummy capacitor 12c is lost, which may cause a reading error between the data element “0” and the data element “1” at the time of the refresh, thus increasing an error rate. Furthermore, because the charges in the parasitic capacity 63 pass in the case of the FRAM shown in FIGS. 3A and 3B, the movement of current greater than I0 is caused to occur at the time of reading the data element “0,” which may cause a reading error between the data element “0” and the data element “1,” thus increasing an error rate. Moreover, the data element “0” and the data element “1” are determined according to the amount of the current accompanied by a change in electric resistance as in the case of the PRAM shown in FIG. 4. Therefore, when the charges in the parasitic capacity 63 are detected as current, a reading error between the data element “0” as the data element “1” may be caused, thus increasing an error rate.
Non-Patent Document 1: “Basic course for VLSI technology” (P37) written by Tadashi Shibata, published by Heibonsha Limited, Publishers
Non-Patent Document 2: “Fujitsu semiconductor device MEMORY MANUAL FRAM guide book” (P20 to P21)
Patent Document 1: JP-A-2006-120810